1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing process thereof, and more particularly, to a semiconductor device and a manufacturing process thereof including a MOS transistor and a bipolar transistor.
2. Description of the Background
Semiconductor devices often include several types of bipolar transistors of different characteristics. For example, a semiconductor memory device requires a plurality of bipolar transistors with different-characteristics in a peripheral circuit region, which includes decoder circuit, buffer circuit, etc, formed around a semiconductor memory circuit region or a memory cell region.
FIG. 1 illustrates a characteristic of a semiconductor device which exhibits changes of current amplification (hfe) and breakdown voltage (BVces, BVceo) against process conditions (axis of abscissa). As seen in FIG. 1, when the breakdown voltage (BVces, BVceo) is made large as shown at a point A of the process condition, the current amplification (hfe) becomes small, while, when the current amplification (hfe) is made large as shown at a point B of the process condition, the breakdown voltage (BVces, BVceo) becomes smaller.
FIG. 2 shows the same characteristic curve as shown above for illustrating a setting of the process condition. FIG. 2 shows a range of process conditions for satisfying both current amplification and breakdown voltage where the current amplification (hfe) exceeds the magnitude required by the design, and the breakdown voltage (BVces, BVceo) begins to exceed the value required by the design.
In a conventional method for manufacturing a semiconductor device including a plurality of bipolar transistors, the same specific kind of the current amplification (hfe) and the breakdown voltage (BVces, BVceo) are obtained for the bipolar transistors simultaneously manufactured. The impurity concentration profile for an emitter, base and collector is optimized so that the breakdown voltage can be assured, and so that the current amplification (hfe) required by the design can be obtained. This process includes an approach to change an emitter profile as shown in FIG. 3a, to change a base profile as shown in FIG. 3b, or to change a collector profile as shown in FIG. 3c. In addition, the size of a bipolar transistor is changed to modify the characteristics depending on the usage. However, the device is becoming constantly miniaturized so that it is getting harder to satisfy both requirements for large current amplification (hfe) and high breakdown voltage.
Accordingly, the objects of the present invention are to solve the above requirements, and to provide an efficient process for manufacturing a semiconductor device which includes bipolar transistors of different characteristics, in a memory circuit region, and/or in a peripheral circuit region, which includes decoder, buffer, etc, formed around the semiconductor memory circuit region or a cell region, in response to the design requirements. The present invention is preferably applied to manufacturing concurrently a memory circuit having MOS transistors such as SRAM memory, and bipolar transistors disposed in its peripheral circuit region and/or in the memory circuit region itself.
According to an aspect of the present invention, there is provided a manufacturing process for a semiconductor device which includes a semiconductor memory circuit region containing semiconductor memories, and a peripheral circuit region disposed around the semiconductor circuit region and containing bipolar transistors. In the process, a plurality of holes are provided selectively in an insulating film of the semiconductor memory circuit region through a resist pattern; and concurrently a plurality of holes are provided selectively in an insulating film of the peripheral circuit region through a resist pattern; and bipolar transistors are formed with characteristics different from each other at the locations of the holes in the peripheral circuit region and/or in the memory circuit region.
In the manufacturing process as set forth above, the bipolar transistors with characteristics different from each other are formed by first forming emitter electrode layers in a plurality of holes in the peripheral circuit region and/or in the memory circuit region, covering the emitter electrode layer in at least one of the holes with a resist, and implanting into the emitter layer in the other of the holes impurity ions to form a different emitter.
Alternatively, as set forth, the bipolar transistors are formed by first forming emitter electrode layers in a plurality of holes in the peripheral circuit region and/or in the memory circuit region, and implanting ions in the electrode layers in a plurality of holes. Then in at least one of the holes, the emitter electrode layer is covered with a resist, and in the other of the holes impurity ions are implanted in an emitter electrode layer to form a different emitter.
In the manufacturing process as set forth above, the bases of the bipolar transistors are formed as follows. While a location of one of a plurality of holes in the peripheral circuit region and/or in the memory circuit region is covered with a resist, impurity ions are implanted in the other of the holes to form a different base.
Alternatively, while one of a plurality of holes in the peripheral circuit region and/or in the memory circuit region is covered with a resist, impurity ions are implanted in the other of the holes to form a different base.
According to another aspect of the present invention as set forth, the bipolar transistors are formed as follows. While one of a plurality of holes in the peripheral circuit region and/or in the memory circuit region is covered with a resist, plural kinds of impurity ions are implanted in the other of the holes to form a different base and a different emitter.
According to another aspect of the present manufacturing process, the bipolar transistors are formed as follows. While at least one location for forming a transistor in the peripheral circuit region is covered with a resist, additional impurity ions are implanted in the other location(s) for forming a transistor in the peripheral circuit region and/or in the memory circuit region to form a different collector region(s) by changing a concentration of impurity in the collector regions.
In another aspect of the manufacturing process as set forth above, the bipolar transistors are formed as follows. While at least one location for forming a transistor in the peripheral circuit region and/or in the memory circuit region is covered with a resist, impurity ions are implanted additionally in the other locations for forming a transistor in the peripheral circuit region to form different collector layer(s) by providing high concentration layer in the collector region(s). Alternatively, the bipolar transistors are formed by covering at least one of a plurality of holes in the peripheral circuit region with a resist, and implanting impurity ions in the other(s) of the holes to form a different collectors.
According to yet another aspect of this invention, the bipolar transistors are formed as follows. While an emitter is formed either by way of implanting ions or diffusing impurity into a base formed either by way of ion implantation or impurity diffusion in one of the holes in the peripheral circuit region and/or in the memory circuit region, an emitter is formed by implanting ions in a well of one conductivity type surrounded by another well of another conductivity type in the other of the holes in the peripheral circuit region and/or in the memory circuit region.
Further, according to the present invention, there is provided a manufacturing process for a semiconductor device which includes a semiconductor memory circuit region containing semiconductor memories, and a peripheral circuit region disposed around the semiconductor memory circuit region, and containing bipolar transistors, in which a plurality of holes are provided selectively in the insulating films through resist patterns in different manufacturing steps in the semiconductor memory region, and a plurality of holes are concurrently provided selectively in the insulating films through resist patterns in correspondence to the different manufacturing steps in the peripheral circuit region, and bipolar transistors are formed with characteristics different from each other at locations of the holes in the peripheral circuit region and/or in the memory circuit region.
In the manufacturing process as set forth above, the bipolar transistors are formed as follows. First, one type of emitter is formed by ion implantation or impurity diffusion in one hole provided in a manufacturing step in the peripheral circuit region and/or in the memory circuit region, then another type of emitter is formed in the other hole provided in another step in the peripheral circuit region and/or in the memory circuit region.
Further, in the manufacturing process as set forth above, at least one of the holes provided in one of a plurality of different manufacturing steps in the peripheral circuit region is covered with a resist, and a different base is formed by implanting impurity ions in the other(s) of the holes formed in another step in the peripheral circuit region.
Further, in the manufacturing process as set forth above, at least one hole provided in one manufacturing step in the peripheral circuit region and/or in the memory circuit region is covered with a resist, and then ion implantation is performed in the other hole(s) provided in another manufacturing step in the peripheral circuit region and/or in the memory circuit region to obtain a different collector.
In the manufacturing process as set forth above, the bipolar transistors are formed as follows. First, an emitter is formed by implanting ions into a base formed by ion implantation or impurity diffusion in one hole provided in one manufacturing step in the peripheral circuit region and/or in the memory circuit region, then a different emitter is formed by implanting ions in a well of one conductivity type surrounded by another well of another conductivity type in the other hole provided in another step in the peripheral circuit region and/or in the memory circuit region.
Although the invention as stated above is directed to the situation where the holes in the memory circuit region and the holes in the peripheral region are formed concurrently, the present invention is also applicable to a manufacturing process including the steps of simultaneously providing a plurality of holes in the peripheral circuit region selectively through a resist pattern; and forming bipolar transistors with characteristics different from each other at the locations of these plurality of holes. In this case, preferably, in manufacturing the memory circuit region and the bipolar transistors in the peripheral circuit region, manufacturing steps other than the hole forming step are also performed as concurrently as possible.
The present invention is also applicable to a manufacturing process including the steps of providing different holes selectively in the insulating film through resist patterns in different manufacturing steps in the peripheral circuit region, and forming bipolar transistors with characteristics different from each other at the locations of these different holes. In this case, preferably, in manufacturing the semiconductor memory circuit region and the bipolar transistors in the peripheral circuit region, manufacturing steps other than the hole forming step are also performed as concurrently and simultaneously as possible.